This work presents an improved input–output (IO) buffer model for signal and power integrity simulation, including power/ground supply voltage (PGSV) variations for the buffer’s input and output stages. Both stages are mathematically modeled from a formulation that is derived from nonlinear electrical circuit analysis, an important aspect that grants these models a good level of generality and, simultaneously, high accuracy. The proposed IO buffer model is linear in the parameters and, therefore, extractable through the linear least-squares technique from the signals acquired in an IO buffer characterization setup. Several validation scenarios, supported on two CMOS driver’s transistor technologies, are performed to evaluate the accuracy of the proposed model. In addition, a comparative analysis is provided, confronting the proposed model’s performance against that of the input/output buffer information specification (IBIS) model, evidencing an outstanding modeling improvement provided by the proposed model.