Embedded redundant array of independent drives (eRAID) architecture was proposed for a high-capacity solid-state drive (SSD) controller, which applies an embedded redundant array of independent drives (RAID) engine to drive and manage an array of independent embedded multimedia card (eMMC) modules. However, the performance of its random access was limited by the eMMC’s uncontrollable timing during data stripping among the eMMC channels. This brief solves this issue using the nonvolatile memory express (NVMe) engine embedded in the controller and a reorganized buffer stripping mechanism. An SSD controller with peripheral component interconnect express (PCIe) Gen $3^{\ast} 4$ Lane interface was designed to verify the capacity and performance, and it was manufactured into a silicon integrated circuit (IC) using a 55-nm semiconductor process. This architecture provides a prospective way to eliminate external dynamic random access memory (DRAM) buffers while maintaining a high random access speed.