Forward error correction (FEC) coding is an indispensable technique in the direct sequence spread spectrum (DS-SS) systems for satellite communication applications. Both the FEC and DS-SS can be regarded as specific cases of probabilistic computing based on analog circuits, which is expected to be a promising solution for power-limited scenarios. The combination of FEC and DS-SS techniques can provide sufficient link margin and robustness for communication systems. In this paper, a probabilistic receiver chain for the Low-Density Parity-Check (LDPC) coded DS-SS system is proposed. Generically, an $m$-sequence can be regarded as a codeword of cyclic linear codes. Similar to the decoding procedure of LDPC codes, the joint detection and decoding process of $m$-sequences can be performed by factor graph-based iterative message-passing algorithms (iMPAs). In terms of the iterative signal processing, we first present an improved approach of iterative stopping criterion which can reduce the average number of iteration by 90% for the LDPC decoding approach. Furthermore, a joint detection and decoding method is developed to provide quick synchronization of the $m$-sequence. Meanwhile, stopping criterion-based iMPAs are especially suitable for analog implementation with low complexity. Finally, cascading to the analog LDPC decoder, the implementation of the $m$-sequence detector is designed. The prototyping chip is fully integrated into a 0.35-$\mu\text{m}$ CMOS technology, which can achieve higher throughput than 3 ${\textbf {Gcps}}$ with a core chip area of 2.79 ${\textbf {mm}}^2$ and power consumption of 6.99 ${\textbf {mW}}$ for its core circuit. Experimental results demonstrate the effectiveness of our proposed receiver mechanism.