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Design and Implementation of High Performance CMOS Cross-Coupled LCVCO for Low Phase Noise | IEEE Conference Publication | IEEE Xplore

Design and Implementation of High Performance CMOS Cross-Coupled LCVCO for Low Phase Noise


Abstract:

This paper proposes a high-performance LCVCO design using CMOS cross-coupled architecture for low phase noise. The design employs an LC tank circuit with a CMOS cross-cou...Show More

Abstract:

This paper proposes a high-performance LCVCO design using CMOS cross-coupled architecture for low phase noise. The design employs an LC tank circuit with a CMOS cross-coupled pair and back-to-back connected NMOS varactor, implemented using CMOS semiconductor technology at 180 nm. The suggested VCO performs in the 16.81–19.22 GHz frequency span and utilizes a 1.8 V voltage source and 1.116 mW consumption of power. The VCO delivers a figure of merit (FoM) of -196.220 dBc/Hz and a phase noise (PN) of -111.022 dBc/Hz at a 1 MHz frequency offset by employing a tail biassing transistor and capacitor. The frequency tuning range (FTR) of the back-to-back coupled NMOS varactor is 13.37%. The Proposed LCVCO to achieved an RMS cycle jitter of 2.4782 fs and a peak-to-peak jitter of 15.31 fs.
Date of Conference: 01-03 September 2024
Date Added to IEEE Xplore: 09 October 2024
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Conference Location: Vellore, India

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