Identifying speed-limiting paths is crucial for design stepping in which problematic paths are fixed or optimized so as to reach higher clock rates. Recently, using at-speed scan test patterns to identify speed-limiting paths has been reported to be a robust and effective solution. In this paper, we propose a systematic approach to find suspect path expressions (SPE) that explain the observed failing and passing bits during at-speed scan testing. These expressions contain comprehensive information, including (1) the pass/fail requirement on each involved path, and (2) the required AND/OR relationships among the involved paths. SPE's can be used to reduce the speed-limiting path suspect set or guide diagnostic pattern generation for further suspect reduction.