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Co-designed systems for deep learning hardware accelerators | IEEE Conference Publication | IEEE Xplore

Co-designed systems for deep learning hardware accelerators


Abstract:

Deep learning has been popularized by its recent successes on challenging artificial intelligence problems. This revolution has been driven by enormous amounts of data, n...Show More

Abstract:

Deep learning has been popularized by its recent successes on challenging artificial intelligence problems. This revolution has been driven by enormous amounts of data, novel machine learning algorithms, and inexpensive, high-performance computing through the cloud. The best solutions skillfully interweave these elements to provide ground breaking advances. This talk will discuss research at Harvard focused on co-designed systems for machine learning. This work can broadly be divided into three major categories: co-design of architectures and algorithms, proof-of-concept chip designs for energy-efficient inference, and characterization/benchmarking of modern deep learning workloads.
Date of Conference: 16-19 April 2018
Date Added to IEEE Xplore: 07 June 2018
ISBN Information:
Electronic ISSN: 2472-9124
Conference Location: Hsinchu, Taiwan

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