Abstract:
In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as t...Show MoreMetadata
Abstract:
In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as the experimental result, the proposed fault model shows efficiency in comparison with corresponding stuck-at fault testing.
Published in: 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
Date of Conference: 07-09 October 2013
Date Added to IEEE Xplore: 25 November 2013
Electronic ISBN:978-1-4799-0524-9
Contents 