Abstract:
In 3D-IC architecture, vertically stacked multiple layer impedes heat dissipation and exacerbates thermal problem especially for reliability degradation. In this paper, w...Show MoreMetadata
Abstract:
In 3D-IC architecture, vertically stacked multiple layer impedes heat dissipation and exacerbates thermal problem especially for reliability degradation. In this paper, we propose a cluster-based reliability- and thermal- aware 3D floorplanning to place modules. We derive a cost function considering both reliability and thermal factors with the balance among the chip of area, wire length, power density and density of STSV in the floorplan. Then we insert rectangle-STSVs and double-STSVs for improving reliability by modified Ford-Fulkerson method. Furthermore, we enhance redundant STSVs insertion rate by RSI algorithm. The experimental results show that more than 80% of single-STSVs can be replaced by rectangle-STSVs or double-STSVs, improving reliability accordingly. After STSV insertion, we construct a precise thermal conduction model to compute temperature distribution and insert TTSVs.Our framework is able to reduce the peak temperature effectively and maintain around 80 °C with minimal TTSVs based on a precise temperature computation model.
Date of Conference: 05-07 October 2015
Date Added to IEEE Xplore: 02 November 2015
ISBN Information: