This paper presents the design of a differential quadrature all-pass filter as a quadrature generator for being used in a phase shifter operating at 19.5 GHz, employing 65 nm CMOS technology. Various solutions have been investigated to address errors occurring in the phase and magnitude of I/Q signals at the output of the quadrature all-pass filter when connected to the next stage. The best result is obtained when combining asymmetry of the network with the inclusion of two additional resistive elements, achieving a quadrature error lower than $2.0^{\circ}$ and a magnitude error lower than of 0.17 from 17 GHz to 22 GHz at the output of the quadrature all-pass filter. As an application, it has been proven that the RMS phase error at the output of a 5-bit active phase shifter has been decreased from $7.6^{\circ}$ to $2.3^{\circ}$.