Abstract:
This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap ...Show MoreMetadata
Abstract:
This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap decision feedback equalizer (DFE) running at quarter rate. While the first 3 DFE taps are implemented by speculation, the latter 12 taps use a switched-cap (SC-DFE) approach. The circuit was produced in 32nm SOI-CMOS, and was measured to receive 30Gb/s PRBS31 data at <;10-12 BER over a 36dB loss channel with an energy efficiency of 3.1mW/Gbps.
Published in: 2012 Symposium on VLSI Circuits (VLSIC)
Date of Conference: 13-15 June 2012
Date Added to IEEE Xplore: 19 July 2012
ISBN Information: