A 16-core processor for software-defined radios is realized in 40nm CMOS. Featuring domain-specific kernels, flexible control and multi-scale interconnects, the processor achieves a peak energy efficiency of 13.1GOPS/mW (76fJ/OP) at 415mV, 25MHz, and a peak performance of 1.17TOPS at 1V, 500MHz, showing >2.4× higher energy efficiency than state-of-the-art communication chip multiprocessors, and closing the gap with functionally-equivalent ASICs to within 2.6×.