Abstract:
A highly digital, low-power, forwarded clock transceiver is presented. It employs source shunt terminated transmit driver and all-digital delay line based I/Q generator b...Show MoreMetadata
Abstract:
A highly digital, low-power, forwarded clock transceiver is presented. It employs source shunt terminated transmit driver and all-digital delay line based I/Q generator based clock deskew suitable for fast wakeup, low-voltage operation. A quad-lane test chip fabricated in 22nm CMOS process operates between 3-to-8 Gbps over a FR4 channel with 12dB loss and achieves BER<;10-12 while consuming 385-to-790fJ/b.
Published in: 2015 Symposium on VLSI Circuits (VLSI Circuits)
Date of Conference: 17-19 June 2015
Date Added to IEEE Xplore: 03 September 2015
Print ISBN:978-4-86348-502-0