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A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS | IEEE Conference Publication | IEEE Xplore

A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS


Abstract:

A highly digital, low-power, forwarded clock transceiver is presented. It employs source shunt terminated transmit driver and all-digital delay line based I/Q generator b...Show More

Abstract:

A highly digital, low-power, forwarded clock transceiver is presented. It employs source shunt terminated transmit driver and all-digital delay line based I/Q generator based clock deskew suitable for fast wakeup, low-voltage operation. A quad-lane test chip fabricated in 22nm CMOS process operates between 3-to-8 Gbps over a FR4 channel with 12dB loss and achieves BER<;10-12 while consuming 385-to-790fJ/b.
Date of Conference: 17-19 June 2015
Date Added to IEEE Xplore: 03 September 2015
Print ISBN:978-4-86348-502-0

ISSN Information:

Conference Location: Kyoto, Japan

References

References is not available for this document.