Abstract:
A 56Gb/s PAM4 wireline transceiver testchip is implemented in 16nm FinFET. The CML transmitter incorporates an auxiliary current injection at the output nodes to maintain...Show MoreMetadata
Abstract:
A 56Gb/s PAM4 wireline transceiver testchip is implemented in 16nm FinFET. The CML transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The receiver consists of continuous-time linear equalizers with constant DC-gain and a 28GSa/s 32-way time-interleaved SAR ADC. The transceiver achieves 1e-8 BER over a backplane channel with 25dB loss at 14GHz while consuming 550mW power, excluding DSP.
Published in: 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)
Date of Conference: 15-17 June 2016
Date Added to IEEE Xplore: 22 September 2016
ISBN Information:
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