This paper proposes a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. Moreover, undesirable oscillation induced by parasitic inductance of interconnects is suppressed by negative inductance technique. A power-efficient divider contributes to save power of the 2^nd-PLL that suppresses output phase noise by the 1 GHz reference. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and −244 dB FOM while consuming 12.7mW.