Abstract:
An asynchronous 48× interleaved SAR ADC optimized for high SNDR above 20 GHz input frequency operating at 20-40 GS/s is presented. The ADC features an 8-channel interleav...Show MoreMetadata
Abstract:
An asynchronous 48× interleaved SAR ADC optimized for high SNDR above 20 GHz input frequency operating at 20-40 GS/s is presented. The ADC features an 8-channel interleaver with clock demultiplexing for enhanced bandwidth, a power- and area-optimized 2-stage SAR ADC, and bandwidth adjustment in the input sampling path. At 32 GS/s and 199 mW power consumption it achieves 47.3 dB SNDR near DC and 37.8 dB at 40 GHz input frequency with a core chip area of 0.16 mm2 in 14 nm FinFET CMOS technology.
Published in: 2018 IEEE Symposium on VLSI Circuits
Date of Conference: 18-22 June 2018
Date Added to IEEE Xplore: 25 October 2018
ISBN Information:
Print on Demand(PoD) ISSN: 2158-5601