A 28Gb/s NRZ wireline transceiver is implemented in 7nm FinFET. A transformer-based LC-PLL sends a single-phase differential clock to the voltage-mode transmitter and the receiver. Local multi-phase clocks are generated in each TX/RX lane to support digital phase interpolation. The receiver equalization consists of a single-stage CTLE that performs both high-frequency peaking and long-tail cancellation, a two-stage programmable gain amplifier, and a 15-tap DFE. The digital CDR achieves <;14ns lock time in a synchronous burst-mode operation. At 28Gb/s, the transceiver achieves <;1E-15 BER over 30dB channel while consuming 283mW.