Abstract:
This paper proposes a prototype downlink I/F employing a tapered-BW daisy-chained topology enabled by a proposed SCM2 technique to exploit the low throughput of NAND I/O,...Show MoreMetadata
Abstract:
This paper proposes a prototype downlink I/F employing a tapered-BW daisy-chained topology enabled by a proposed SCM2 technique to exploit the low throughput of NAND I/O, which allows a NAND controller to handle 32 NAND PKGs on a single I/F channel. The fabricated I/F achieved 12.8 Gb/s with BER of 10−12 while consuming 252.1 mW for a TX and 375.7 mW for four RXs. The FoM is 409.6 PKG·Gb/s.
Published in: 2018 IEEE Symposium on VLSI Circuits
Date of Conference: 18-22 June 2018
Date Added to IEEE Xplore: 25 October 2018
ISBN Information:
Print on Demand(PoD) ISSN: 2158-5601