In this work, we present an ultra-low voltage SRAM compiler targeting small to medium array sizes to provide a smaller area solution compared to conventional 6T -based SRAMs. A 12T write contention and read upset free bit-cell is used in the design. Array architecture employs a read-modify-write scheme to support bit-write masking and column multiplexing. Built-in-self-test (BIST) and synchronous write-through (SWT) options are also supported to provide testability features while power management (PM) option is included to provide low-leakage sleep and shut-down modes. Proposed design is fabricated in 7nm FinFET technology and achieves lowest reported Vmin of 290mV in this technology.