Abstract:
This paper presents a wideband and energy-efficient single-loop 3rd order CTSDM enabled by an ELD-SAB-Merged integrator and a 3-stage opamp. We utilize only a single DAC ...Show MoreMetadata
Abstract:
This paper presents a wideband and energy-efficient single-loop 3rd order CTSDM enabled by an ELD-SAB-Merged integrator and a 3-stage opamp. We utilize only a single DAC and opamp to accomplish the ELD compensation in the SAB structure. While featuring a PSQ technique and a 1st order NS-SAR, the 28nm prototype achieves a 74.4dB SNDR in a 50MHz BW and consumes 10.4mW with 171.2dB FoMS.
Published in: 2020 IEEE Symposium on VLSI Circuits
Date of Conference: 16-19 June 2020
Date Added to IEEE Xplore: 10 August 2020
ISBN Information:
Contents 