Loading [a11y]/accessibility-menu.js
A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS | IEEE Conference Publication | IEEE Xplore
Scheduled Maintenance: On Tuesday, 25 February, IEEE Xplore will undergo scheduled maintenance from 1:00-5:00 PM ET (1800-2200 UTC). During this time, there may be intermittent impact on performance. We apologize for any inconvenience.

A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS


Abstract:

This work presents an NRZ receiver (RX) implementation for microprocessor application in 7nm FinFET CMOS technology. It covers data rate from 25 to 50Gb/s and features on...Show More

Abstract:

This work presents an NRZ receiver (RX) implementation for microprocessor application in 7nm FinFET CMOS technology. It covers data rate from 25 to 50Gb/s and features on-chip AC coupling to support a wide input common-mode range. The RX includes two identical banks with their own clock and data recovery (CDR) to dynamically tackle parameter drift over time. A quarter-rate 3-tap fully speculative decision feedback equalizer (DFE) opens eyes over channel with 30dB insertion loss. Current-mode logic (CML) based clock path boasts three degrees of freedom of phase adjustment and random jitter (RJ) attenuation to broaden the eyes. At 0.9V supply the energy efficiency is 2.22pJ/b with 28% eye opening (BER=10-12) at 50Gb/s with PRBS31 and channel loss of 20dB.
Date of Conference: 16-19 June 2020
Date Added to IEEE Xplore: 10 August 2020
ISBN Information:

ISSN Information:

Conference Location: Honolulu, HI, USA

References

References is not available for this document.