Abstract:
A side-channel-attack (SCA) resistant AES engine with multiplicative-masked Sboxes is fabricated in Intel 4 CMOS, achieving 1.8× lower area overhead compared to conventio...Show MoreMetadata
Abstract:
A side-channel-attack (SCA) resistant AES engine with multiplicative-masked Sboxes is fabricated in Intel 4 CMOS, achieving 1.8× lower area overhead compared to conventional additive-masked implementations. Balanced dual-rail detector circuits pre-empt zero-value attacks while providing a 34,000× increase in side-channel-attack resistance, with a measured minimum-traces-to-disclose (MTD) of 850M encryption traces.
Date of Conference: 12-17 June 2022
Date Added to IEEE Xplore: 22 July 2022
ISBN Information: