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Medusa: A 0.83/4.6 <span class="MathJax_Preview">{\mu}\mathrm{J}</span><script type="math/tex" id="MathJax-Element-1">{\mu}\mathrm{J}</script>/Frame 86/91.6%-CIFAR-10 TinyML Processor with Pipelined Pixel Streaming of Bottleneck Layers in 28nm CMOS | IEEE Conference Publication | IEEE Xplore

Medusa: A 0.83/4.6 {\mu}\mathrm{J}/Frame 86/91.6%-CIFAR-10 TinyML Processor with Pipelined Pixel Streaming of Bottleneck Layers in 28nm CMOS


Abstract:

Medusa is a 28 nm programmable 8-bit processor that achieves state-of-the-art inference energy across a range of always-on tiny Machine Learning (tinyML) tasks. It featur...Show More

Abstract:

Medusa is a 28 nm programmable 8-bit processor that achieves state-of-the-art inference energy across a range of always-on tiny Machine Learning (tinyML) tasks. It features custom 6T-latch-based Inner Loop Memories (ILMs) optimized for tinyML that achieve a read energy of 15 fJ/Byte, and its Pipelined Pixel Streaming (PPS) architecture leverages ILMs to reduce system-level memory access energy by up to 9.5x. Medusa performs inference image-to-label, with native support for critical tinyML operations, including memory-intensive depthwise separable convolution-based bottleneck layers. It achieves 0.83/4.6 μl/Frarnc at a latency of 0.6/2.6 ms and an accuracy of 86.2/91.6% on CIFAR-10, advancing the state-of-the art in inference energy by 3.4x/4.9x. In addition, it achieves 0.23 μJ/Frame at 0.27 ms and 90.8% on Google Speech Commands and 5.0 μ J /Frame and 3.8 ms at 81.5% on Visual Wake Words.
Date of Conference: 16-20 June 2024
Date Added to IEEE Xplore: 26 August 2024
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Conference Location: Honolulu, HI, USA

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