In this paper, we propose a new ultra low-power flip-flop circuit structure that supports true single phase clock operation and conditional capture characteristics. Simulation results based on 7nm Fin-FET process shows 63% power reduction while reducing cell area by 7%, compared to the conventional transmission-gate flip-flop. Silicon measure based on a test chip shows successful operation even at 0.33V, proving its structural robustness near sub-threshold region.