Abstract:
The paper presents enhanced architectures of pseudo-random test pattern generators and on-chip test data decompressors based on ring generators. The new structures are ai...Show MoreMetadata
Abstract:
The paper presents enhanced architectures of pseudo-random test pattern generators and on-chip test data decompressors based on ring generators. The new structures are aimed at improving their layout and routing properties while at the same time reducing propagation delays introduced by associated phase shifters.
Published in: 22nd IEEE VLSI Test Symposium, 2004. Proceedings.
Date of Conference: 25-29 April 2004
Date Added to IEEE Xplore: 18 May 2004
Print ISBN:0-7695-2134-7
Print ISSN: 1093-0167