Summary form only given. Test cost needs of industry are supported by EDA historically through various ATPG technologies. Initially, it was through static compression, which is done as a post pattern generation step. Static compression involves re-ordering of patterns with fault simulation to identify any redundant patterns as well as to identify pattern combining options. Second generation of scan test time reduction is done through dynamic compression in which ATPG engine attempts to combine patterns during pattern generation stage. Then industry focus has shifted to ?scan compression? architectures in which additional logic is added to generate required care bits for wider scan channels without increasing tester channels, which in-turn helps to reduce chain length and hence reduce scan load time. In today's tape-outs of designs, it is common to see compression ratio of scan vectors is in the order of 100. Higher compression solutions tend to peak out toggle activity within the design and test power may become a limiting factor. Power-aware ATPG solutions exist today to limit the toggle activity during both shift and capture which can be used to solve test power challenges but come at the expense of increased test cost. In today's multi-voltage and multi-power domain designs, test scheduling based on designer's power intent is critical to cover test for all user-power states and for optimizing test time. During this planning phase, it is important to weigh the trade-off between power dissipation and test application time as both constraints need to be optimized concurrently. In this case, the right number of power domains will need to be tested at the same time as oppose to one domain at a time or all domains powered on. In this talk, we review the impact of today's power consumption related challenges on test automation, and then, we propose a practical solution based on a multi-mode DFT architecture that enables efficient test scheduling. We will cover how we de...