Process variations and aging effects are proven to have significant impact on paths delay in integrated circuits as technology continues to scale. Identification of the critical paths to test, in a low-cost manner, during both manufacturing and infield tests is thus a challenging task. In this paper, we propose a methodology for identifying testable representative paths (TRPs). The maximum mean delay and variance of the TRPs closely follow the maximum mean delay and variance of all critical paths in the circuit. TRPs, a small subset of critical paths, are selected using a novel QR decomposition-based algorithm taking into account circuit topology, process variations, and aging effects. Our results show up to 70.87% and 60.77% reduction in total number of critical paths and path delay fault (PDF) patterns, respectively.