Abstract:
A systematic method is proposed for automatically identifying positive feedback loops (PFLs) in analog/mixed-signal circuits. The method first converts the netlist of a c...Show MoreMetadata
Abstract:
A systematic method is proposed for automatically identifying positive feedback loops (PFLs) in analog/mixed-signal circuits. The method first converts the netlist of a circuit into a directed dependency graph (DDG) which captures the critical relationships among branch currents and node voltages. It then utilizes graph theory techniques to find all feedback loops from the DDG and finally, criterion are developed to determine the PFLs. Since multiple states is caused by the PFLs, this method could identify the circuit's vulnerability to undesigned operating points only by its structure without the computation of DC solutions. The proposed approach is implemented in program and simulation results show it could identify all the PFLs very robustly.
Published in: 2014 IEEE 32nd VLSI Test Symposium (VTS)
Date of Conference: 13-17 April 2014
Date Added to IEEE Xplore: 22 May 2014
Electronic ISBN:978-1-4799-2611-4