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Thwarting timing attacks on NEMS relay based designs | IEEE Conference Publication | IEEE Xplore

Thwarting timing attacks on NEMS relay based designs


Abstract:

NEMS relay technology is a promising class of emerging devices that offer zero static leakage and hence overcomes the power dissipation issues of deep-submicron CMOS tech...Show More

Abstract:

NEMS relay technology is a promising class of emerging devices that offer zero static leakage and hence overcomes the power dissipation issues of deep-submicron CMOS technology devices. As NEMS relay based digital circuits have potentially higher energy-efficiency than those based on CMOS transistors, circuits based on NEMS relay device are worth exploring. However, NEMS relay devices suffer from large delay compared to CMOS technology; Binary Decision Diagram (BDD) based implementation targets to minimize the total circuit delay, fixing this problem. However, such an implementation renders the timing delay of a NEMS based circuit input-dependent, which can be exploited to infer on-chip secret information from delay information. In this presentation, we illustrate these security vulnerabilities and present countermeasures for a recently proposed energy-efficient block cipher Midori128 that has an on-chip secret key that needs to be protected.
Date of Conference: 25-27 April 2016
Date Added to IEEE Xplore: 26 May 2016
ISBN Information:
Electronic ISSN: 2375-1053
Conference Location: Las Vegas, NV, USA

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