Abstract:
Industry continues to grapple with analog test in terms of the right set of parameters to be tested and the right set of tests and measurements required for them. On one ...Show MoreMetadata
Abstract:
Industry continues to grapple with analog test in terms of the right set of parameters to be tested and the right set of tests and measurements required for them. On one hand, is the growing analog content in today's ICs, and on the other, is the need to optimise test and characterization to make it affordable and timely across different quality and reliability requirements laid down by the application markets. Different companies and teams have often used their own internal custom methods to simplify analog test with varying demands on test and automation, resulting in varying degrees of success. In this innovative practices session, the three presentations are from three leading semiconductor companies, and they illustrate their approach to simplifying analog test. They cover different topics ranging from enablers for adoption of structural test methods to how the ATE can scale to match with the DUT high speed interfaces, and the modifications needed in the test flow to leverage the results from new validation and BIST methods.
Published in: 2017 IEEE 35th VLSI Test Symposium (VTS)
Date of Conference: 09-12 April 2017
Date Added to IEEE Xplore: 18 May 2017
ISBN Information:
Electronic ISSN: 2375-1053