Abstract:
This paper presents a high-performance, low-cost, and double node upset (DNU) tolerant latch design. The latch mainly constructs from a 3-input Muller C-element at the ou...Show MoreMetadata
Abstract:
This paper presents a high-performance, low-cost, and double node upset (DNU) tolerant latch design. The latch mainly constructs from a 3-input Muller C-element at the output stage and a single node upset resilient cell for keeping data, and the cell mainly consists of triple mutual feedback 2-input Muller C-elements, thus the latch is DNU tolerant. Using fewer CMOS transistors, clock gating technique, and high-speed transmission path, the latch also performs with lower cost penalties. Simulation results have demonstrated the DNU tolerability and a ~97.78% area-power-delay product saving for the latch design on average compared with the DNU tolerant latch designs.
Published in: 2017 IEEE 35th VLSI Test Symposium (VTS)
Date of Conference: 09-12 April 2017
Date Added to IEEE Xplore: 18 May 2017
ISBN Information:
Electronic ISSN: 2375-1053