Hardware acceleration for Artificial Intelligence (AI) is now a very competitive and rapidly evolving market. As a result, fast time-to-market is a leading concern for this segment. To speed up time-to-market and ensure quality, new design-for-test (DFT) architectures, new DFT methodologies and technologies are emerging. AI chips are typically very big with many identical and non- identical cores, distributed memories, high-speed IOs, which makes testing of such a gigantic SoC a very challenging task. We found it is very important for us to understand these new challenges from the point of views of DFT engineers. In this innovative practice session, we invited three DFT experts from three AI chip companies to share their experiences of DFT on AI chips.