Abstract:
At the system-level, cores are put together using interconnects that we refer to as high-level communication links. This paper presents an abstract interconnect model for...Show MoreMetadata
Abstract:
At the system-level, cores are put together using interconnects that we refer to as high-level communication links. This paper presents an abstract interconnect model for cores connecting to each other to estimate, and thus model, crosstalk noise resulting from the physical properties of interconnects. Such models consider the effects of adjacent wires on each other in the form of weighted transitions. Transition weights are extracted by DC analysis of interconnect SPICE models. These weights form our raw-models, which are then specialized by AC analysis of RLC interconnect models in a mixed-signal simulation environment. The latter analyses establish weight thresholds for glitch faults. Our simulations show that if we were to use only DC-based models for crosstalk faults, we would be over / under-estimating faults as compared with models that are specialized by AC simulation runs. For higher data rates, Specialized models perform an order of magnitude better than DC-based models for crosstalk fault detection.
Published in: 2020 IEEE 38th VLSI Test Symposium (VTS)
Date of Conference: 05-08 April 2020
Date Added to IEEE Xplore: 04 June 2020
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