Abstract:
This paper proposes an innovative design methodology for layout-friendly decompressor used in EDT compression architecture. A segmented decompressor architecture is propo...Show MoreMetadata
Abstract:
This paper proposes an innovative design methodology for layout-friendly decompressor used in EDT compression architecture. A segmented decompressor architecture is proposed, in which each segment drives a subset of scan chains. The EDT input channel injectors are carefully selected to maximize the encoding capacity for all scan chains. Experimental results with several large industrial designs demonstrate that using the proposed technology, the routing congestion introduced by EDT decompressor is reduced significantly with negligible impact on test coverage and improved pattern count.
Published in: 2020 IEEE 38th VLSI Test Symposium (VTS)
Date of Conference: 05-08 April 2020
Date Added to IEEE Xplore: 04 June 2020
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