The paper discusses the challenges that memory testing faces in the era of Gate-All-Around transistor technology and proposes a solution concept to overcome them. With the transition from two-dimensional to three-dimensional transistors, and in particular with the advent of FinFET, many new factors have entered the scene, creating a need for new testing techniques capable of coping with the complexity of novel memory designs. However, the end of the FinFET era and the beginning of a new Gate-All-Around design paradigm means that these methods need to be revisited to ensure they remain effective and in line with the latest transistor technologies that are contenders to replace FinFET. The paper assesses the test challenges associated with the Gate-All-Around technology and proposes a solution concept that sets a vector for a thorough investigation of underlying defects, fault modeling, and the development of efficient test and repair algorithms.