Wear-out reliability in integrated circuits is becoming an increasingly complex topic, with emerging high-reliability markets demanding stricter requirements, diverse workloads making stress characterization challenging, and sub-5nm device scaling aggravating variability in degradation processes. Efforts to tackle these complexities can benefit greatly from sophisticated techniques that effectively capture the variable and uncertain nature of semiconductor wear-out mechanisms. True-to-life stochastic modelling and computational Bayesian inference offer promising avenues in this pursuit but are difficult to leverage without a framework for specifying and evaluating wear-out models that capture this probabilistic information. We present a temporal wear-out simulator, Gerabaldi, as a foundation for enabling these statistical techniques for integrated circuit reliability engineering. The simulator introduces novel capabilities including layered stochastic parameter modelling, fully agnostic design enabling custom degradation model and stress test specifications, and wear-out model definition forms compatible with modern computational Bayesian inference frameworks. Here, we frame Gerabaldi within the context of existing wear-out analysis methods. We then present its key design features and two detailed example applications to illustrate the simulator’s capabilities.