Projective Geometry (PG) based Low Density Parity Check (LDPC) codes have many useful properties, including easy encoding and decoding by simple majority logic technique. With these useful features, they can be useful error control codes in future. In this paper, we present three novel architectures comprising of one parallel and two semi-parallel decoder architectures for popular PG-based LDPC codes. These architectures have no memory clash and further are reconfigurable for different lengths (and their corresponding rates). The three architectures can be configured either for the regular belief propagation based decoding or majority logic decoding (MLD).