This paper presents the performance of a manifold multiplexer circuit implemented in a 65 nm CMOS process for use in a high data rate transceiver. Two channels are configured in a manifold structure with coupled-line bandpass filters. The filter center frequency channels are at 180 GHz and 315 GHz. The diplexer was designed in ANSYS HFSS and measured using WR-5 and WR-3 waveguide modules. Undeembedded measurements show 9 dB of insertion loss. When parasitics are accounted for in post simulation modeling the measured IL is closer to 5 dB with 40 GHz bandwidth for the 180 GHz design.