Dual-Vt FPGA design for leakage power reduction (abstract only)

Leakage power has been overshadowed by dynamic power minimization techniques in FPGAs, and is a growing concern in programmable logic. This paper proposes a dual threshold voltage implementation of the FPGA architecture for leakage power reduction. A CAD flow is developed for assigning high threshold voltage to the logic elements within the logic blocks of the FPGA for leakage power reduction. The CAD flow ensures that all the logic blocks remain identical with respect to the number of high and low threshold voltage logic elements that each logic block contains. This CAD flow leads to a dual threshold voltage implementation for the FPGA architecture. Results indicate that over 95% of the logic elements in the FPGA can be assigned high threshold voltage. On an average leakage savings of 60% and up to 70% for some benchmarks can be achieved. The proposed CAD flow forms a basis on which other dual threshold voltage implementations of FPGA can be evaluated. We investigate the design trade-offs between the ratio of the number of high and number of low-Vt logic elements in a cluster and the leakage savings. We also investigate the impact of cluster size on leakage savings for the dual threshold voltage implementation.