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A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only)

Published:20 February 2005Publication History

ABSTRACT

Numerous applications in Digital Signal Processing (DSP), telecommunications, graphics, cryptography and control systems have computations that involve a large number of multiplications of one variable with one or several constants. In this paper, we present a constant array multiplier core generator using dynamic partial evaluation. The proposed constant array multiplier core generator combines a new partial evaluation method named Full Complement Recoding with Booth's recoding and the straightforward partial evaluation method. Based on the number of 0s, the number of runs that have more than two consecutive 1s and the total number of 1s in all the runs in the constant operand, the proposed multiplier core generator selects one of the three partial evaluation methods to construct a partial evaluation architecture and generate an efficient Hardware Description Language (HDL) code that can be used as a design component. The constant multiplier core generated by the Xilinx CORE GeneratorTM system does not provide the optimized constant multipliers for a large number of cases. When implemented using Xilinx FPGA Virtex II device, the average area saving and delay improvement of the constant multiplier generated by proposed core generator is 70% and 36% compared to the 55% and 15% of constant multipliers generated by Xilinx CORE GeneratorTM system.

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  • Published in

    cover image ACM Conferences
    FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
    February 2005
    288 pages
    ISBN:1595930299
    DOI:10.1145/1046192

    Copyright © 2005 ACM

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    • Published: 20 February 2005

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