Saraju P. Mohanty
N. Ranganathan
Abstract
Recently, dynamic frequency scaling has been explored at the CPU and system levels for power optimization. Low-power datapath scheduling using multiple supply voltages has been well researched. In this work, we develop new datapath scheduling algorithms that use multiple supply voltages and dynamic frequency clocking in a coordinated manner in order to reduce the energy consumption of datapath circuits. In dynamic frequency clocking, the functional units can be operated at different frequencies depending on the computations occurring within the datapath during a given clock cycle. The strategy is to schedule high-energy units, such as multipliers at lower frequencies, so that they can be operated at lower voltages to reduce energy consumption and the low-energy units, such as adders at higher frequencies, to compensate for speed. The proposed time- and resource-constrained algorithms have been applied to various high-level synthesis benchmark circuits under different time and resource constraints. The experimental results show significant reduction in energy for both the algorithms.
- Antola, A., Piuri, V., and Sami, M. 1998. A low-redundancy approach to semi-concurrent error detection in datapaths. In Proceedings of the Design Automation and Test in Europe. 266--272.]] Google Scholar
- Benini, L., Macii, E., Pnocino, M., and Micheli, G. D. 1998. Telescopic units : A new paradigm for performance optimization of VLSI design. IEEE Trans. Comput.-Aid. Des. Integrat. Circ. Syst. 17, 3 (Mar.), 220--232.]] Google Scholar
- Benini, L., Micheli, G. D., Lioy, A., Macii, E., Odasso, G., and Poncino, M. 1999. Automatic synthesis of large telescopic units based on near-minimum timed supersetting. IEEE Trans. Comput. 48, 8 (Aug.), 769--779.]] Google Scholar
- Brynjolfson, I. and Zilic, Z. 2000a. Dynamic clock management for low power applications in FPGAs. In Proceedings of the IEEE Custom Integrated Circuits Conference. 139--142.]]Google Scholar
- Brynjolfson, I. and Zilic, Z. 2000b. FPGA clock management for low power. In Proceedings of the International Symposium on FPGAs. 219--219.]] Google Scholar
- Burd, T. and Brodersen, R. W. 1995. Energy efficient CMOS microprocessor design. In Proceedings of the 28th Hawaii International Conference on System Sciences. 288--297.]] Google Scholar
- Burd, T., Pering, T. A., Stratakos, A. J., and Brodersen, R. W. 2000. A dynamic voltage scaled microprocessor system. IEEE J. Solid-State Circ. 35, 11 (Nov.), 1571--1580.]]Google Scholar
- Chang, J. M. and Pedram, M. 1997. Energy minimization using multiple supply voltages. IEEE Trans. VLSI Syst. 5, 4 (Dec.), 436--443.]] Google Scholar
- Fetweis, G., Chiu, J., and Fraenkel, B. 1993. A low-complexity bit-serial DCT/IDCT architecture. In Proceedings of the IEEE International Conference on Communications. 217--221.]]Google Scholar
- Grunwald, D., Levis, P., and Farkas, K. I. 2000. Policies for dynamic clock scheduling. In Proceedings of the 2000 Operating Systems Design and Implementation.]] Google Scholar
- Hsu, C. H., Kremer, U., and Hsiao, M. 2000. Compiler-directed dynamic frequency and voltage scheduling. In Proceedings of the Workshop on Power-Aware Computer Systems. 65--81.]] Google Scholar
- Johnson, M. and Roy, K. 1997. Datapath scheduling with multiple supply voltages and level converters. ACM Trans. Des. Automat. Electron. Syst. 2, 3 (July), 227--248.]] Google Scholar
- Kim, J. M. and Chae, S. I. 1996. New MPEG2 decoder architecture using frequency scaling. In Proceedings of the IEEE International Symposium on Circuits and Systems. 253--256.]]Google Scholar
- Kollig, P. and Al-Hashimi, B. M. 1997. Simultaneous scheduling, allocation and binding in high level synthesis. IEE Electron. Lett. 33, 18 (Aug.), 1516--1518.]]Google Scholar
- Kumar, A. and Bayoumi, M. 1999. Multiple voltage-based scheduling methodology for low power in the high level synthesis. In Proceedings of the International Symposium on Circuits and Systems (Vol. 1). 371--379.]]Google Scholar
- Lin, Y. R., Hwang, C. T., and Wu, A. C. H. 1997. Scheduling techniques for variable voltage low power design. ACM Trans. Des. Automat. Electron. Syst. 2, 2 (Apr.), 81--97.]] Google Scholar
- Manzak, A. and Chakrabarti, C. 2002. A low power scheduling scheme with resources operating at multiple voltages. IEEE Trans. VLSI Syst. 10, 1 (Feb.), 6--14.]] Google Scholar
- Martin, T. L. and Siewiorek, D. P. 2001. Nonideal battery and main memory effects on CPU speed-setting for low power. IEEE Trans. VLSI Syst. 9, 1 (Feb.), 29--34.]] Google Scholar
- Micheli, G. D. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York, NY.]] Google Scholar
- Mohanty, S. P. and Ranganathan, N. 2003. Energy efficient scheduling for datapath synthesis. In Proceedings of the International Conference on VLSI Design. 446--451.]] Google Scholar
- Mohanty, S. P., Ranganathan, N., and Chappidi, S. K. 2003. An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. In Proceedings of the International Symposium on Circuits and Systems (Vol. 5). 313--316.]]Google Scholar
- Mohanty, S. P., Ranganathan, N., and Krishna, V. 2002. Datapath scheduling using dynamic frequency clocking. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI. 65--70.]] Google Scholar
- Monteiro, J., Devadas, S., Ashar, P., and Mauskar, A. 1996. Scheduling techniques to enable power management. In Proceedings of the ACM/IEEE Design Automation Conference. 349--352.]] Google Scholar
- Musoll, E. and Cortadella, J. 1995. Scheduling and resource binding for low power. In Proceedings of the 8th International Symposium on System Synthesis. 104--109.]] Google Scholar
- Papachristou, C. A. and Konuk, H. 1990. A linear program driven scheduling and allocation method. In Proceedings of the 27th ACM/IEEE Design Automation Conference. 77--83.]] Google Scholar
- Pedram, M. 1996. Power minimization in IC design: Principles and applications. ACM Trans. Des. Automat. Electron. Syst. 1, 1 (Jan.), 3--56.]] Google Scholar
- Pering, T., Burd, T., and Brodersen, R. W. 2000. Voltage scheduling in the lpARM microprocessor system. In Proceedings of the International Symposium on Low Power Electronics and Design. 96--101.]] Google Scholar
- Pouwelse, J., Langendoen, K., and Sips, H. 2001a. Dynamic voltage scaling on a low-power microprocessor. In Proceedings of the 7th International Conference on Mobile Computing Network.]] Google Scholar
- Pouwelse, J., Langendoen, K., and Sips, H. 2001b. Energy priority scheduling for variable voltage processor. In Proceedings of the International Symposium on Low Power Electronics and Design. 28--33.]] Google Scholar
- Ranganathan, N., Vijaykrishnan, N., and Bhavanishankar, N. 1998. A linear array processor with dynamic frequency clocking for image processing applications. IEEE Trans. Circ. Syst. Video Techn. 8, 4 (Aug.), 435--445.]] Google Scholar
- Sarrafzadeh, M. and Raje, S. 1999. Scheduling with multiple voltages under resource constraints. In Proceedings of the IEEE Symposium on Circuits and Systems (Vol. 1). 350--353.]]Google Scholar
- Shiue, W. T. and Chakrabarti, C. 2000. Low-power scheduling with resources operating at multiple voltages. IEEE Trans. Circ. Syst.-II: Analog Digital Signal Process. 47, 6 (June), 536--543.]]Google Scholar
Index Terms
- Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
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