Jayaram Mudigonda
ABSTRACT
In this study, we refute the popular belief [1,2] that packet processing does not benefit from data-caching. We show that a small data-cache of 8KB can bring down the packet processing time by much as 50-90%, while reducing the off-chip memory bandwidth usage by about 60-95%. We also show that, unlike general-purpose computing, packet processing, due to its memory-intensive nature, cannot rely exclusively on data-caching to eliminate the memory bottleneck completely.
- D. Comer. Network Systems Design Using Network Processors. Prentice Hall, ISBN 0-13-141792-4, 2003. Google Scholar
Digital Library
- P. C. Lekkas. Network Processors: Architectures, Protocols and Platforms. McGraw-Hill Profesional, 1 edition, July 2003. Google ScholarDigital Library
- J. Mudigonda, H. M. Vin, and R. Yavatkar. Managing Memory Access Latency in Packet Processing Systems. Technical Report TR-05-11, University of Texas at Austin, 2005.Google Scholar
Index Terms
- Managing memory access latency in packet processing
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Managing memory access latency in packet processing
Performance evaluation reviewIn this study, we refute the popular belief [1,2] that packet processing does not benefit from data-caching. We show that a small data-cache of 8KB can bring down the packet processing time by much as 50-90%, while reducing the off-chip memory bandwidth ...
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ANCS '05: Proceedings of the 2005 ACM symposium on Architecture for networking and communications systemsOverhead of memory accesses limits the performance of packet processing applications. To overcome this bottleneck, today's network processors can utilize a wide-range of mechanisms-such as multi-level memory hierarchy, wide-word accesses, special-...
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