Physical design challenges for multi-million gate SoC's: an STMicroelectronics perspective

This talk addresses current and future physical design methodology evolution for large complex System-on-Chip like Set Top Box devices within STMicroelectronics. Set Top Boxes have become one of the fastest growing segments of home electronics market. Set Top Box devices are built around an On Chip Bus which connects the internal processor with the audio processing, video processing, security, and communication units. These units are composed of elementary IP (Intellectual Property) blocks. The number and complexity of such units vary depending on the market segment to be addressed, from low-end to high-end devices. Overall circuit complexity varies from 2 Million instances to 5+ Million instances. Process choice, ranging now from 130nm to 65nm, must be approached in the context of the consumer market, where cost and time to market are the dominant factors.Historically, limited hardware and software capabilities led to physical integration of the chip with a "low granularity" hierarchical manner, almost IP block centric. Top down approach was used, integrating mostly soft IP blocks. The efficiency in terms of silicon utilization was quite limited, but integration process was simple.Moving to fast 64 bits workstations, the hardware limit dropped, allowing grouping of more blocks together, showing the need to rethink the physical partitioning process, also linked to more demanding On Chip Bus performances.One of the key aspects of this approach is to isolate logical and physical hierarchies, which allows taking advantage of platform based design tools for the front-end design capture, and gives more flexibility to physical design. Focus was placed on partitioning process, and especially the impact on the On Chip Bus micro architecture, budgeting and prototyping. Crucial challenges remain in top level hierarchical clock distribution and multimode/multi-corner convergence. Overall productivity increases due to limited number of physical partitions.New tools capabilities allow now to think doing such circuits flat, but is this always a good solution? The choice has to be made considering maturity of the RTL, risks of last minute changes, predictable runtimes for implementation, and parallelism of the physical design process (time to market impact).Today the perceived best solution is a mix of hierarchical design for initial physical database creation, and flat final optimization. The details of such a hybrid approach will be presented in this talk.