Andrew B. Kahng
Bao Liu
ABSTRACT
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significant as multiple-input switching on gate delay variation [2]. We establish a functional relationship between driver gate delay and crosstalk alignment by deterministic circuit simulation, and derive closed form formulas for statistical distributions of driver gate delay and output signal arrival time.Our proposed method can be smoothly integrated into a static timing analyzer, which runtime is dominated by sampling deterministic delay calculation, while probabilistic computation and updating take constant time. Our experimental results on 70nm technology global interconnect structures and 130nm technology industry designs show respectively 159:4% and 147:4% differences in mean and standard deviation of gate delay without crosstalk aggressor alignment consideration, while our method gives within 2:57% and 3:86% offset in gate output signal arrival time mean and standard deviation, respectively.
- A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Statistical Timing Analysis Using Bounds," in Proc. Design, Automation, and Test in Europe, 2003, pp. 62--68. Google Scholar
Digital Library
- A. Agarwal, F. Dartu and D. Blaauw, "Statistical Gate Delay Model Considering Multiple Input Switching," in Proc. Design Automation Conference, 2004, pp. 658--663. Google ScholarDigital Library
- K. Agarwal, D. Sylvester, D. Blaauw, F. Liu, S. Nassif and S. Vrudhula, "Variational Delay Metrics for Interconnect Timing Analysis," in Proc. Design Automation Conference, 2004, pp. 381--384. Google ScholarDigital Library
- Berkeley Predictive Technology Model, http://www-device.eecs.berkeley.edu/~ptm/.Google Scholar
- V. Khandelwal and A. Srivastava, "A General Framework for Accurate Statistical Timing Analysis Considering Correlations," in Proc. Design Automation Conference, 2005, pp. 89--94. Google ScholarDigital Library
- Y. Liu, L. T. Pileggi and A. J. Strojwas, "Model Order-Reduction of RC(L) Interconnect Including Variational Analysis," in Proc. Design Automation Conference, 1999, pp. 201--206. Google ScholarDigital Library
- J. D. Ma and R. A. Rutenbar, "Interval-Valued Reduced Order Statistical Interconnect Modeling," in Proc. Intl. Conference on Computer Aided Design, 2004, pp. 460--467. Google ScholarDigital Library
- F. N. Najm and N. Menezes, "Statistical Timing Analysis Based on a Timing Yield Model," in Proc. Design Automation Conference, 2004, pp. 460--465. Google ScholarDigital Library
- A. Odabasioglu, M. Celik and L. T. Pileggi, "PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 8, August 1998, pp. 645--654. Google ScholarDigital Library
- M. Orshansky, A. Bandyopadhyay, "Fast statistical timing analysis handling arbitrary delay correlations," in Proc. Design Automation Conference, 2004, pp. 337--342. Google ScholarDigital Library
- M. Orshansky, K. Keutzer, "A general probabilistic framework for worst case timing analysis," in Proc. Design Automation Conference, 2002, pp. 556--561. Google ScholarDigital Library
- M. Orshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, pp. 544--553. Google ScholarDigital Library
- Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo, "Driver Modeling and Alignment for Worst-Case Delay Noise," in Proc. Design Automation Conference, 2001, pp. 720--725. Google ScholarDigital Library
- S. K. Tiwary and R. A. Rutenbar, "Scalable Trajectory Methods for On-Demand Analog Macromodel Extraction," in Proc. Design Automation Conference, 2005, pp. 403--408. Google ScholarDigital Library
- C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, "First-Order Incremental Block-Based Statistical Timing Analysis," in Proc. Design Automation Conference, 2004, pp. 331--336. Google ScholarDigital Library
Index Terms
- Statistical gate delay calculation with crosstalk alignment consideration
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