ABSTRACT
Two programmable FFT processors for OFDM (Orthogonal Frequency Division Multiplex) communication systems are presented in this paper. Coolay-Tukey radix-2/4/8 algorithm and mixed-radix-2/22/23 are employed in the pipelined SDF (Single-path Delay Feedback) architecture and pipelined MDC (Multiple-Path Delay Commutator) shared-memory architecture, respectively. The size of FFT processors with power of 2 can be programmable in the range between 64 and 8192. Based on the programmable SDF architecture, an FFT processor with 64/128-point has been implemented under the TSMC 0.35mm CMOS technology. Its core area is 1.6*1.6mm2 and the power consumption is 340mW. Moreover, a simple addressing scheme for pipelined MDC shared-memory architecture with mixed-radix algorithm is also proposed to achieve the programmable object. It can provide a simple control circuit for memory addressing generation, and the mixed-radix butterfly sequence can be automatically generated by way of simple counter. In addition, for the N-point FFT processor, only N/8 coefficients should be stored in the VLSI implementation, therefore, the ROM size and the FFT processor area are reduced. According to the simple control scheme and smaller memory size, the low-power VLSI architecture can be achieved. Furthermore, the architecture with the mixed-radix algorithm also enhances the speed in performing large-point FFT computations compared with the existing shared-memory architectures. Based on this architecture, not only high radix-23 butterfly is adopted to achieve the requirement of high throughput, but also low radix-22 or radix-2 butterfly is utilized to allow all of FFT calculation for N=2n. An VLSI architecture of 8192-point FFT processor with only power consumption of 890mW is also implemented to demonstrate the proposed method.
- William Y. Zou and Yiyan Wu, "COFDM: An OverView" IEEE Transactions on Broadcasting , Vol. 41, No. 1, pp. 1--8, March 1995.Google ScholarCross Ref
- Richard Van Nee, "A New OFDM Standard for High Rate Wireless LAN in the 5 GHZ Band", IEEE Vehicular Technology Conference, 1999, pp. 258--262.Google Scholar
- Lihong Jia, Yonghong Gao, and Hannu Tenhunen, "Efficient VLSI Implementation of Radix-8 FFT Algorithm", IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 1999, pp. 468--471.Google Scholar
- Lihong Jia, Yonghong Gao, and Hannu Tenhunen, "A New VLSI-Oriented FFT Algorithm and Implementation", IEEE International ASIC Conference, 1998, pp. 337--341.Google Scholar
- Shousheng He and Mats Torkelson, "Designing Pipeline FFT Processor for OFDM (de)Modulation" 1998 URSI International Symposium on Signals, Systems, and Electronics, pp.257--262.Google Scholar
- Ching-Hsien Chang, Chin-Liang Wang, and Yu-Tai Chang, "Efficient VLSI Architectures for Fast Computation of the Discrete Fourier Transform and Its Inverse," IEEE Transactions on Signal Processing, vol. 48, Issue.11, pp.3206--3216, Nov. 2000. Google ScholarDigital Library
- Yutai Ma and Lars Wanhammar, "A Hardware Efficient Control of Memory Addressing for High-Performance FFT Processors," IEEE Transactions on Signal Processing, vol. 48, Issue 3, pp. 917--921, March 2000. Google ScholarDigital Library
- Yutai Ma, "An Effective Memory Addressing Scheme for FFT Processors," IEEE Transactions on Signal Processing, vol. 47, Issue 3, pp. 907--911, March 1999. Google ScholarDigital Library
Index Terms
- VLSI implementation of programmable FFT architectures for OFDM communication system
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