Luca Sterpone
ABSTRACT
Nowadays Field Programmable Gate Arrays (FPGAs) are an improved technology for developing high-performance embedded systems. SRAM-based FPGAs offers the possibility of in-the-field reconfiguration that results in the ability to adapt the product to modified user's requirements, to enrich the product's features, or simply to correct bugs. With the advent of multi-million gate FPGAs, the size of the configuration information that defines what circuit the FPGA implements has increased drastically, and thus the amount of external memory needed to keep the configuration data is increasing dramatically. In this work we developed a novel configuration compression system that exploits internal configuration mechanism of modern SRAM-based FPGAs and results in high compression efficiency. The proposed system is applicable to any modern SRAM-based FPGA devices having an embedded microprocessor core since the configuration data are processed as raw data. Moreover, the proposed approach does not require any external hardware support and allows high speed dynamic reconfiguration. Experimental results on Xilinx SRAM-based FPGAs platform implementing several real-world circuits demonstrated 82% savings in memory on the average.
- K. Compton and S. Hauck, "Reconfigurable computing: a survey of systems and software," ACM Computing Surveys, 34(2), pp. 171--210, June 2002. Google Scholar
Digital Library
- Xilinx Product Specification, "Virtex-II Platform FPGAs: Complete Data Sheet," DS031 (v3.4) March 1, 2005.Google Scholar
- A. Khu, "Xilinx FPGA Configuration Data Compression and Decompression," Xilinx - WP152, September 2001.Google Scholar
- Z. Li and S. Hauck, "Configuration compression for Virtex FPGAs," IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 111--119, 2001. Google ScholarDigital Library
- S. Hauck, Z. Li and E. J. Schwabe, "Configuration compression for the Xilinx XC6200 FPGA," IEEE Transactions on Computer Aided Des. Integr. Circuits Syst., vol. 18, pp. 1107--1113, August 1999. Google ScholarDigital Library
- J. Pan, T. Mitra and W. Wong, "Configuration bitstream compression for dynamically reconfigurable FPGAs," IEEE/ACM International Conference on Computer Aided Design, pp. 766--773, November 2004. Google ScholarDigital Library
- A. Dandalis and V. K. Prasanna, "Configuration Compression for FPGA-based embedded systems," IEEE Transactions on VLSI systems, vol. 13, no. 12, December 2005. Google ScholarDigital Library
- A. Le, "Simplifying the FPGA Configuration Design Process," Xilinx White Paper: Platform Flash PROMs, WP253, v1.0.1, August 2006.Google Scholar
- Altera sheets, "Using Altera Enhanced Configuration Devices," Chapter 14, April 2003.Google Scholar
- M. Hübner, M. Ullmann, F. Weissel, J. Becker, "Real-time configuration code decompression for dynamic FPGA self-reconfiguration", 18th IEEE International Parallel and Distributed Processing Symposium, pp. 138, April 2004.Google Scholar
- M. Ullmann, M. Hübner, B. Grimm, J. Becker, "An FPGA Run-Time System for Dynamical On-Demand Reconfiguration," 18th IEEE International Parallel and Distributed Processing Symposium, pp. 135, April 2004.Google Scholar
- Atmel FPGA, www.atmel.comGoogle Scholar
- Xilinx FPGA, www.xilinx.comGoogle Scholar
- Atmel Corporation, "AT94K Series Field Programmable System Level Integrated Circuit," 2001.Google Scholar
- V. Eck, P. Kalra, R. LeBlanc and J. McManus, "In-Circuit Partial Reconfiguration of Rocket-IO Attributes," Xilinx Application Notes, XAPP662, May 26, 2004.Google Scholar
- A. Moffat, R. M. Neal and I. H. Witten, "Arithmetic Coding Revisited," ACM Transactions on Information Systems, 16(3): 256--294, July 1998. Google ScholarDigital Library
- Xilinx Product Specification, "Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet," DS083 v4.5, October 10, 2005.Google Scholar
- Xilinx Reference Guide, "PowerPC Processor," EDK 6.1, September 2, 2003.Google Scholar
Index Terms
- A new decompression system for the configuration process of SRAM-based FPGAS
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