Abstract
For an FPGA designer, several choices are available in terms of target FPGA devices, IP-cores, algorithms, synthesis options, runtime reconfiguration, degrees of parallelism, among others, while implementing a design. Evaluation of design alternatives in the early stages of the design cycle is important because the choices made can have a critical impact on the performance of the final design. However, a large number of alternatives not only results in a large number of designs, but also makes it a hard problem to efficiently manage, simulate, and evaluate them. In this article, we present a framework for FPGA-based application design that addresses the aforementioned issues. This framework supports a hierarchical modeling approach that integrates application and device modeling techniques and allows development of a library of models for design reuse. The framework integrates a high-level performance estimator for rapid estimation of the latency, area, and energy of the designs. In addition, a design space exploration tool allows efficient evaluation of candidate designs against the given performance requirements. The framework also supports extension through integration of widely used tools for FPGA-based design while presenting a unified environment for different target FPGAs. We demonstrate our framework through the modeling and performance estimation of a signal processing kernel and the design of end-to-end applications.
- Actel. 2007. Actel ProASICPLUS---The nonvolatile reprogrammable gate array. http://www.actel.com/products/proasicplus/default.aspx.Google Scholar
- Almagor, L., Cooper, K., Grosul, A., Harvey, T., Reeves, S., Subramanian, D., Torczon, L., and Waterman, T. 2004. Finding effective compilation sequences. In Proceedings of the Conference on Language Compilers and Tools for Embedded Systems. Google ScholarDigital Library
- Altera. 2007. Altera Stratix, Stratix-II, hardcopy. http://www.altera.com/products/devices/.Google Scholar
- Bazargan, K., Kastner, R., Ogrenci, S., and Sarrafzadeh, M. 2000. A C to hardware/software compiler. In Proceedings of the Conference on Field-Programmable Custom Computing Machines. Google ScholarDigital Library
- Benini, L., Bogliolo, A., and Micheli, G. 2000. A survey of design techniques for system-level dynamic power management. In IEEE Trans. Very Large Scale Integration Syst. 8, 3. Google ScholarDigital Library
- Bhattacharyya, S., Murthy, P., and Lee, E. A. 1999. Synthesis of embedded software from synchronous dataflow specifications. J. Very Large Scale Integration Signal Proc. Syst. 21, 2. Google ScholarDigital Library
- Bondalapati, K. and Prasanna, V. K. 2000. Loop pipelining and optimization for reconfigurable architectures. In Proceedings of the Reconfigurable Architectures Workshop. Google ScholarDigital Library
- Celoxica Limited. 2005. The Handel-C language. http://www.celoxica.com/.Google Scholar
- Choi, S., Govindu, G., Jang, J., and Prasanna, V. K. 2003. Energy-Efficient and parameterized designs for fast Fourier transform on FPGAs. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing.Google Scholar
- Choi, S., Jang, J., Mohanty, S., and Prasanna, V. K. 2002. Domain-Specific modeling for rapid system-wide energy estimation of reconfigurable architectures. J. Supercomput. 26, 3 (Nov.), 259--261. Google ScholarDigital Library
- Devlin, M. 2003. Product focus DSP: How to make smart antenna arrays. Xcell J. Q1.Google Scholar
- Dick, C. 2003. FPGA: Enabling the software/reconfigurable radio. In Proceedings of the 14th International Conference on Field-Programmable Logic and Applications (Antwerp, Belgium, Aug.--Sept.). Lecture Notes in Computer Science, vol. 3203. Springer Verlag.Google Scholar
- Doucet, F., Otsuka, M., Shukla, S., and Gupta, R. 2002. An environment for dynamic component composition for efficient co-design. In Proceedings of the Conference on Design Automation and Test in Europe. Google ScholarDigital Library
- Ghiasi, S., Nahapetian, A., and Sarrafzadeh, M. 2004. An optimal algorithm for minimizing runtime reconfiguration delay. ACM Trans. Embedded Comput. Syst. 3, 2 (May), 237--256. Google ScholarDigital Library
- Guo, Z., Najjar, W., Vahid, F., and Vissers, K. 2004. A quantitative analysis of the speedup factors of FPGAs over processors. In Proceedings of the Symposium on Field-Programmable Gate Arrays. Google ScholarDigital Library
- IBM. 2007. PowerPC 405 embedded cores. http://www-3.ibm/com/chips/techlib/techlib.nsf/products/PowerPC_405_Emb%edded_Cores.Google Scholar
- Intel. 2007. PXA 255 processor. http://www.intel.com/design/intelxscale/.Google Scholar
- Jang, J., Choi, S., and Prasanna, V. K. 2002. Energy-Efficient matrix multiplication on FPGAs. In Proceedings of the Field Programmable Logic and Applications. Google ScholarDigital Library
- Johnston, W., Hanna, J., and Millar, R. J. 2004. Advances in dataflow programming languages. ACM Comput. Surv. 36, 1. Google ScholarDigital Library
- Jones, A., Bagchi, D., Pal, S., Tang, X., Choudhary, A., and Banerjee, P. 2002. PACT HDL: A C compiler with power and performance optimizations. In Proceedings of the Conference on Compilers, Architectures and Synthesis for Embedded Systems. Google ScholarDigital Library
- Kirk, D., Roper, M., and Wood, M. 2002. Defining the problems of framework reuse. In Proceedings of the Computer Software and Applications Conference. Google ScholarDigital Library
- Ledeczi, A., Davis, J., Neema, S., and Agrawal, A. 2003. Modeling methodology for integrated simulation of embedded systems. ACM Trans. Model. Comput. Simul. 13, 1 (Jan.), 82--103. Google ScholarDigital Library
- Lee, E. A. and Messerschmitt, D. G. 1987. Synchronous data flow. Proc. IEEE 75.Google Scholar
- Maestre, R., Kurdahi, F., Fernandez, M., Hermida, R., Bagherzadeh, N., and Singh, H. 2001. A framework for reconfigurable computing: Task scheduling and context management. IEEE Trans. Very Large Scale Integration Des. 9, 6, 858--873. Google ScholarDigital Library
- Mamidipaka, M., Khouri, M., Dutt, N., and Abadir, M. 2003. IDAP: A tool for high level power estimation of custom array structures. In Proceedings of the Conference on Computer Aided Design. Google ScholarDigital Library
- McGregor, G., Robinson, D., and Lysaght, P. 1998. Hardware/Software co-design environment for reconfigurable logic systems. In Proceedings of the Conference on Field-Programmable Logic and Applications. Google ScholarDigital Library
- Mentor Graphics. 2007a. Seamless hardware/software co-verification and FPGA advantage. http://www.mentor.com/fpga-advantage/.Google Scholar
- Mentor Graphics. 2007b. ModelSim. http://www.model.com/.Google Scholar
- Milan. 2007. Model-Based integrated simulation. http://milan.usc.edu/.Google Scholar
- Mohanty, S. and Prasanna, V. 2003. A hierarchical approach for energy efficient application design using heterogeneous embedded systems. In Proceedings of the Conference on Compilers, Architectures and Synthesis for Embedded Systems. 243--254. Google ScholarDigital Library
- Mohanty, S. and Prasanna, V. 2004. An algorithm designer's workbench for platform FPGAs. In Proceedings of the Conference on Field Programmable Logic and its Application.Google Scholar
- Mohanty, S., Prasanna, V. K., Neema, S., and Davis, J. 2002. Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation. In Proceedings of the Conference on Language Compilers and Tools for Embedded Systems. Google ScholarDigital Library
- Mukherjee, R. and Memik, S. 2004. Power-Driven design partitioning. In Proceedings of the Conference on Field Programmable Logic and its Application.Google Scholar
- Ou, J., Choi, S., and Prasanna, V. K. 2003. Performance modeling of reconfigurable SoC architectures and energy-efficient mapping of a class of applications. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines. Google ScholarDigital Library
- Prasanna, V. K. and Tsai, Y. 1991. On synthesizing optimal family of linear systolic arrays for matrix multiplication. IEEE Trans. Comput. 40, 6, 770--774. Google ScholarDigital Library
- Shang, L. and Jha, N. K. 2001. High-Level power modeling of CPLDs and FPGAs. In Proceedings of the International Conference on Computer Design. Google ScholarDigital Library
- Shenoy, N., Choudhary, A., and Banerjee, P. 2001. An algorithm for synthesis of large time-constrained heterogeneous adaptive systems. ACM Trans. Des. Autom. Electron. Syst. 2, 6, 207--225. Google ScholarDigital Library
- Shirazi, N., Luk, W., and Cheung, P. 1998. Automating production of run-time reconfigurable designs. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines. Google ScholarDigital Library
- SimpleScalar. 2007. The SimpleScalar tool set. http://www.simplescalar.com/.Google Scholar
- Singer, P. 2002. The optimal detector. In SPIE Conference: Signal and Data Processing for Small Targets.Google Scholar
- Software Integrated Systems. 2006. GME-4. Generic Modeling Environment. http://www.isis.vanderbilt@edu/Projects/gme/.Google Scholar
- Srivastava, N., Trahan, J., Vaidyanathan, R., and Rai, S. 2003. Adaptive image filtering using run-time reconfiguration. In Proceedings of the Reconfigurable Architectures Workshop. Google ScholarDigital Library
- Stammermann, A., Kruse, L., Nebel, W., Pratsch, A., Schmidt, E., Schulte, M., and Schulz, A. 2001. System level optimization and design space exploration for low power. In Proceedings of the International Symposium on System Synthesis. Google ScholarDigital Library
- Synopsis. 2007. Synopsis design compiler FPGA. http://www.synopsys.com/fpga/.Google Scholar
- SystemC. 2007. SystemC HDL. http://www.systemc.org/.Google Scholar
- Sztipanovits, J. and Karsai, G. 1999. Model-Integrated computing. IEEE Comput. Mag. 30, 4 (Apr.), 110--111. Google ScholarDigital Library
- Xilinx. 2007a. Xilinx system generator for Simulink (Matlab). http://www.xilinx.com/products/software/sysgen/product_details.htm.Google Scholar
- Xilinx. 2007b. Xilinx Virtex-II and Virtex-II Pro. http://www.xilinx.com/.Google Scholar
Index Terms
- A model-based extensible framework for efficient application design using FPGA
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