Liu Xianhua
ABSTRACT
For many embedded applications, program code size is a critical design factor for its relationship with limited memory, energy and communication bandwidth. While pursuing better code redundancy elimination in compilation time, people also began to focus on better encoding. Some RISC processors, such as ARM, MIPS and UniCore, support a 32bit/16bit dual-width instruction set. Mixed code generation is introduced in expectation of achieving both higher code density from the 16-bit instruction set and good performance from the 32-bit one, with little extra cost.
We describe a new fine-grained mixed code generation scheme in this paper. We introduce into the 32-bit ISA a new 16-bit Mode-Changing instruction set which has the following features: firstly, the operation of the instructions are very common in UniCore32 programs and are appropriate to be coded into 16 bits; secondly, they can switch the current processor mode while performing their own operations. We implement the mixed code generation at link time in our compilation toolchain. Our experiments show that this scheme is successful in better encoding a program's computations to reduce code size without sacrificing performance. In addition, there are little modifications to micro-architecture, ensuring good compatibility with the original instruction set architecture.
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Index Terms
- Efficient code size reduction without performance loss
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