A. Mariano
ABSTRACT
Modern front-end receivers perform direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The final aspiration is to directly digitize the RF signal and hence eliminate any RF/analog mixers. In order to direct digitize the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these specifications, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) to be used as a quantizer in modern digital receivers. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sample rate in a 0.8-2GHz bandwidth.
- A. Mariano, D. Dallet, Y. Deval, J-B. Bégueret, "4GHz Continuous-Time Bandpass Delta-Sigma Modulator for Directly High-IF A/D Conversion", IEEE SBCCI 2006, pp. 103--107, Ouro Preto-Brazil, August 2006. Google Scholar
Digital Library
- J. A. Cherry, W. M. Snelgrove, W. Gao, "On the Design of a Fourth-Order Continuous-time LC Delta-Sigma Modulator for UHF A/D Conversion", IEEE Transactions on Circuits and System, vol. 47, No 6, June 2000.Google Scholar
- W. Gao, J. A. Cherry, W. M. Snelgrove, "A 4GHz fourth-order SiGe HBT band pass DS modulator", in Proc. VLSI Circuits Symposium., pp. 174--175,1998.Google Scholar
- A. Mariano, D. Dallet, Y. Deval, J-B. Bégueret, "High-IF Sampling Continuous-Time Bandpass Delta-Sigma Modulator", IEEE PRIME 2006, pp. 129--132, june 12-15, Otranto-Italy, 2006.Google Scholar
- C. Recoquillon, J. B. Begueret, Y. Deval, G. Montignac, A. Baudry, "A 4Gsps, 2-4 GHz Input Bandwidth, 3-bits Flash A/D Converter", ICECS 2004, Tel-Aviv, Israel, 2004.Google Scholar
- W. Gao, W.M. Snelgrove and S.J. Kovacic, "A 5 GHz SiGe HBT Return to Zero Comparator for RF A/D Conversion", IEEE Journal of Solid-State Circuits, Vol. 31, n°10, pp. 1502--1506, Oct 1996.Google Scholar
- B. Prégardier, U. Langmann and W.J. Hillery, "A 1.2 GS/s 8-b Silicon Bipolar Track&Hold IC", IEEE Journal of Solid-State Circuits, Vol. 3, n°°09, pp. 1336--1339, Sept 1996.Google Scholar
- T. Baumheinrich, B. Prégardier and U. Langmann, "A 1 Gsample/s Full Nyquist Silicon Bipolar Track&Hold IC", IEEE Journal of Solid-State Circuits, Vol. 32, n°°12, pp. 1951--1960, Dec 1997.Google Scholar
- K. Poulton, K.L. Knudsen, J.J. Corcoran, K-C Wang, R.B. Nubling, R.L. Pierson, M-C. Chang, P.M. Asbeck and R.T. Huang, "A 6-B 4Gs/s GaAs HBT ADC", IEEE Journal of Solid-State Circuits, Vol. 30, n°10, pp. 1109--1115, Oct 1995.Google ScholarCross Ref
- D.Meiling, R. Jia, Z. Xianmin, C. Kangsheng, " The encoder/decoder based on parallel FBGs in optical CDMA system" , Info-tech and Info-net, 2001. Proceedings pp. 688--692. Beijing--China, 2001Google Scholar
Index Terms
- High-speed CMOS analog-to-digital converter for front-end receiver applications
Recommendations
Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications
Digital front-end receivers realize direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The trend is to eliminate any RF/...
CMOS flash analog-to-digital converter for high speed and low voltage applications
GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSIA CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flash ADC can be applied to low supply voltage. A fat tree encoder that has ...
A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter
This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power ...
Comments