Leomar Soares da Rosa
Andre Inacio Reis
ABSTRACT
The performance of CMOS gates is strongly dependent on the number of transistors in series in both pull-up PMOS and pull-down NMOS networks. In this paper, two approaches presenting the minimum number of stacked devices are compared, using conventional series-parallel CMOS as a reference. The proposed analysis takes into consideration different lists of cells, including standard cell libraries used in regular (fixed library) technology mapping or functions generated by software in library-free technology mapping. The quality of the transistor networks in consideration is evaluated according to device count, worst case transistor stack, as well as logical effort of the network. The relationship between such topologies and technology mapping is also discussed.
- T.Uehara, W.M. vanCleemput. "Optimal Layout of CMOS Functional Arrays. IEEE Transactions on Computers, Vol. 30-5, May 1981, pp. 305--312. Google Scholar
Digital Library
- F.R.Schneider, R.P.Ribas, S.S.Sapatnekar, A.I.Reis, "Exact lower bound for the number of switches in series to implement a combinational logic cell". ICCD 2005, pp. 357--362. Google ScholarDigital Library
- F.R.Schneider, A.I.Reis, "Fast CMOS Logic Style Using Minimum Transistor Stack for Pull-up and Pull-down Networks". IWLS 2006, pp. 134--141.Google Scholar
- B.S.Carlson, C.Y.R.Chen, U.Singh. "Optimal cell generation for dual independent layout styles". IEEE Transactions on CAD, Vol. 10--6, Jun. 1991, pp. 770--782.Google ScholarDigital Library
- M.A.Riepe and K.A.Sakallah. "Transistor placement for non-complementary digital VLSI cell synthesis". ACM TODAES, Vol. 8-1, Jan. 2003, pp. 81--107. Google ScholarDigital Library
- T.Iizuka, M.Ikeda and K.Asada. "Exact Minimum-Width Transistor Placement for Dual and Non--Dual CMOS Cells". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, no. 12, Dec. 2005, pp. 3485--3491. Google ScholarDigital Library
- C.Yang and M.Ciesielski. "BDS: a BDD-based logic optimization system". IEEE Transactions on CAD, Vol. 21-7, Jul. 2002, pp. 866--876. Google ScholarDigital Library
- P.Buch, A.Narayan, A.R.Newton and A.Sangiovanni-Vincentelli. "Logic synthesis for large pass transistor circuits". ICCAD 1997, pp. 663--670. Google ScholarDigital Library
- C.Scholl and B.Becker. "On the generation of multiplexer circuits for pass transistor logic". DATE 2000, pp. 372--378. Google ScholarDigital Library
- P.Lindgren, M.Kerttu, M.Thornton and R.Drechsler. "Low power optimization technique for BDD mapped circuits". ASP-DAC 2001, pp. 615--621. Google ScholarDigital Library
- R.S.Shelar and S.S.Sapatnekar. "An efficient algorithm for low power pass transistor logic synthesis". ASP-DAC 2002, pp. 87--92. Google ScholarDigital Library
- M.Avci and T.Yildirim. "General design method for complementary pass transistor logic circuits". Electronics Letters, Vol. 39--1 , Jan. 2003, pp. 46--48.Google Scholar
- R.S.Shelar and S.S.Sapatnekar. "BDD decomposition for delay oriented pass transistor logic synthesis". IEEE Transactions on VLSI Systems, Vol. 13--8, Aug. 2005, pp. 957--970. Google ScholarDigital Library
- A.I.Reis, M.Robert, D.Auvergne and R.Reis. "Associating CMOS transistors with BDD arcs for technology mapping". Electronics Letters, Vol. 31--14, 1995, pp. 1118--1120.Google ScholarCross Ref
- S.Gavrilov, A.Glebov, S.Pullela, S.C.Moore, A.Dharchoudhury, R.Panda, G.Vijayan and D.T.Blaauw. "Library-less synthesis for static CMOS combinational logic circuits". ICCAD 1997, pp. 658--662. Google ScholarDigital Library
- C.L.Liu and J.A.Abraham. "Transistor level synthesis for static CMOS combinational circuits". GLSVLSI, 1999, pp. 172--175. Google ScholarDigital Library
- S.Gavrilov and A.Glebiy. "BDD based circuit level structural optimization for digital CMOS". MALOPD 1999, pp. 45--49.Google Scholar
- M.Kanecko and J.Tian. "Concurrent cell generation and mapping for CMOS logic circuits". ASPDAC97, pp. 247--52.Google Scholar
- R.E.B.Poli, F.R.Schneider, R.P.Ribas and A.I.Reis. "Unified theory to build cell-level transistor networks from BDDs". SBCCI 2003, pp. 199--204. Google ScholarDigital Library
- L.S.da Rosa Jr., F.Marques, T.M.G.Cardoso, R.P.Ribas, S.S.Sapatnekar, A.I.Reis, "Fast Transistor Networks from BDDs". SBCCI 2006, pp. 137--142. Google ScholarDigital Library
- L.S.da Rosa Jr., F.Marques, T.M.G.Cardoso, R.P.Ribas, A.I.Reis. "BDDs and transistor networks with minimum pull-up/pull-down chains". IWLS 2006, pp. 142--149.Google Scholar
- I.Sutherland, B.Sproull and D.Harris, Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, 1999. Google ScholarDigital Library
- E.M.Sentovich, K.J.Singh, L.Lavagno et al. "SIS : A system for sequential circuit synthesis". Technical report UCB/ERL M92/41, University of California at Berkeley, 1992.Google Scholar
- F.S.Marques, L.S.da Rosa Jr., R.P.Ribas, S.Sapatnekar, A.I.Reis. "DAG Based Library-Free Technology Mapping". GLSVLSI 2007, pp. 293--298. Google ScholarDigital Library
- D.Kagaris and T.Haniotakis. "A Methodology for Transistor-Efficient Supergate Design". IEEE Transactions on VLSI, Vol. 15-4, Apr. 2007, pp. 488--492. Google ScholarDigital Library
Index Terms
- A comparative study of CMOS gates with minimum transistor stacks
Recommendations
Fast disjoint transistor networks from BDDs
SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems designIn this paper, we describe different ways to derive transistor networks from BDDs. The use of disjoint pull-up (composed of PMOS transistors) and pull-down (composed of NMOS transistors) planes allows simplifications that result in shorter pull-up and ...
Modeling and estimating leakage current in series-parallel CMOS networks
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSIThis paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis. ...
Delay analysis of CMOS gates using modified logical effort model
In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the ...
Comments