ABSTRACT
Integrating circuits in the vertical direction can alleviate interconnect related problems and enable heterogeneous chips to be stacked in a single package with a small form factor. This paper addresses the power delivery issues in 3D chips revealing some interesting facts and design challenges. A multi-story power delivery technique that can reduce the worst case DC noise by 45% and lower the overhead power consumed in the power supply network by 65% is proposed. A test chip layout in an SOI process, showing a 5.3% area overhead, demonstrates the feasibility of the scheme.
- K. Banerjee, S. Souri, P. Kapur, K. Saraswat, "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration", Proc. of the IEEE, pp. 602--633, May 2001.Google ScholarCross Ref
- K. Bernstein, P. Andry, J. Cann, et al., "Interconnects in the Third Dimension: Design Challenges for 3D ICs", Design Automation Conference, pp. 562--567, June 2007. Google ScholarDigital Library
- K. Takahashi, M. Sekiguchi, "Through Silicon Via and 3-D Wafer/Chip Stacking Technology", VLSI Circuits Symposium, pp. 89--90, June 2006.Google Scholar
- J. Burns, B. Aull, C. Chen, et al., "A Wafer-Scale 3-D Circuit Integration Technology", IEEE Trans. on Electron Devices, Vol. 53, pp. 2507--2516, Oct. 2006.Google ScholarCross Ref
- H. Hua, C. Mineo, K. Shoenfliess, et al., "Exploring Compromises among Timing, Power and Temperature in Three-Dimensional Integrated Circuits", Design Automation Conference, pp. 997--1002, June 2006. Google ScholarDigital Library
- B. Goplen, S. Sapatnekar, "Placement of 3D ICs with Thermal and Interlayer Via Considerations", Design Automation Conference, pp. 626--631, June 2007. Google ScholarDigital Library
- J. Cong, Y. Zhang, "Thermal via Planning for 3-D ICs", International Conference on Computer Aided Design, pp. 745--752, Nov. 2005. Google ScholarDigital Library
- C. Abebei, H. Mogal, K. Bazargan, "Three-dimensional Place and Route for FPGAs", Asian Pacific Design Automation Conference, pp. 713--718, Jan. 2005. Google ScholarDigital Library
- S. Das, A. Chandrakasan, R. Reif, "Design tools for 3D integrated circuits", Asian Pacific Design Automation Conference, pp. 53--56, Jan. 2003. Google ScholarDigital Library
- A. Fazzi, R. Canegallo, L. Ciccarelli, et al., "3D Capacitive Interconnects with Mono and Bi-Directional Capabilities", International Solid-State Circuits Conference, pp. 356--357, Feb. 2007Google Scholar
- Q. Gu, Z. Xu, J. Ko, "Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICs", International Solid-State Circuits Conference, pp. 448--449, Feb. 2007.Google Scholar
- K. Kanda, D. Antono, K. Ishida, et al., "1.27GB/s/pin 3mW/pin Wireless Superconnect (WSC) Interface Scheme", International Solid-State Circuits Conference, pp. 186--187, Feb. 2003.Google Scholar
- L. Feihui, C. Nicopoulos, T. Richardson, et al., "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory", International Symposium on Computer Architecture, pp. 130--141, 2006. Google ScholarDigital Library
- R. Mahajan, R. Nair, V. Wakharkar, et al., "Emerging Directions for Packaging Technologies," Intel Technology Journal, vol. 6, no. 2, pp. 62--75, May 2002.Google Scholar
- J. Gu, C. Kim, "Multi-Story Power Delivery for Supply Noise Reduction and Low Voltage Operation", International Symposium on Low Power Electronics and Design, pp. 192--197, Aug. 2005.S. Google ScholarDigital Library
- Rajapandian, K. Shepard, P. Hazucha, and T. Karnik, "High-Tension Power Delivery: Operating 0.18μm CMOS Digital Logic at 5.4V", International Solid-State Circuits Conference, pp. 298--299, 2005.Google Scholar
Index Terms
- A multi-story power delivery technique for 3D integrated circuits
Recommendations
Scaling trends of on-chip power distribution noise
The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced ...
Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies
3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, renders the design of 3-D power delivery a challenge. We investigate in this paper ...
Cost-effective power delivery to support per-core voltage domains for power-constrained processors
DAC '12: Proceedings of the 49th Annual Design Automation ConferencePer-core voltage domains can improve performance under a power constraint. Most commercial processors, however, only have one chip-wide voltage domain because splitting the voltage domain into per-core voltage domains and powering them with multiple off-...
Comments